An Efficient Design Approach for a Prime-length Generalized Hartley Transform Systolic Array

An efficient approach to the design of a VLSI array for a prime-length type III generalized discrete Hartley transform (GDHT) is presented. The design makes use of an appropriate decomposition of the GDHT into two half-length circular correlation structures having the same length and form that can be concurrently computed and implemented on a single linear systolic array using some of the known hardware sharing techniques. As a consequence, a substantial increase in computational speed with a simplified control structure and low hardware complexity can be achieved, while preserving all the advantages, such as the low I/O and hardware costs, of the circular correlation based VLSI implementations.